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Disambiguation of "Tarawneh, Ghaith"

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Language and hardware acceleration backend for graph processing.

, , , , , , , , and . FDL, page 1-7. IEEE, (2017)

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Monther Tarawneh

Mohamed Fayez Tarawneh

Mohamed Fayez Tarawneh

Hussein al- Tarawneh

Mohamed Fayez Tarawneh

 

Other publications of authors with the same name

Significance-Driven Logic Compression for Energy-Efficient Multiplier Design., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 417-430 (2018)Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools., and . ASYNC, page 43-50. IEEE Computer Society, (2018)Approximate adder segmentation technique and significance-driven error correction., , , , and . PATMOS, page 1-6. IEEE, (2017)Adaptive Synchronization for DVFS Applications., and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 93-102. Springer, (2012)An FPGA-based hardware accelerator for simulating spatiotemporal neurons., and . ICECS, page 618-621. IEEE, (2014)Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression., , , , , and . SiPS, page 1-6. IEEE, (2017)Energy-efficient approximate multiplier design using bit significance-driven logic compression., , , , and . DATE, page 7-12. IEEE, (2017)Collaborative Content Creation: Impact of Media Type on Author Behavior., , , and . CSCW Companion, page 341-344. ACM, (2018)Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture., , , , , , , , and . IET Comput. Digit. Tech., 16 (2-3): 71-88 (2022)An RTL method for hiding clock domain crossing latency., and . ICECS, page 540-543. IEEE, (2012)