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Disambiguation of "Jang, Jaemin"

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Refresh-Aware Write Recovery Memory Controller.

, , , , , , and . IEEE Trans. Computers, 66 (4): 688-701 (2017)

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Tae-Seok Jang

Liem Khiem Jang

Saeed Jangani

Eun-Ju Jang

Hee-Kwon Jang

 

Other publications of authors with the same name

Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory., , , , and . IEEE Trans. Computers, 68 (5): 752-764 (2019)Rank-Level Parallelism in DRAM., , , , , , and . IEEE Trans. Computers, 66 (7): 1274-1280 (2017)A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (2): 141-145 (2016)Multiple clone row DRAM: a low latency and area optimized DRAM., , , , , , and . ISCA, page 223-234. ACM, (2015)DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells., , and . IEEE Trans. Computers, 68 (12): 1741-1754 (2019)Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs., , , , , and . IEEE Trans. Computers, 67 (10): 1403-1415 (2018)A new application-layer overlay platform for better connected vehicles., , and . IJDSN, (2017)Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation., , , , , , , and . IEEE Trans. Computers, 65 (7): 2213-2227 (2016)DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing., , , , , , and . IEEE Trans. Computers, 65 (10): 3027-3040 (2016)In-DRAM Data Initialization., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (11): 3251-3254 (2017)