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Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments.

, , , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 56 (2): 1163-1171 (2020)

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Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS., , , , , , , and . IEEE Trans. Emerg. Top. Comput., 9 (1): 520-533 (2021)Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS., , , , and . ATS, page 86-91. IEEE, (2018)Design of a Novel Self-Recoverable SRAM Cell Protected Against Soft Errors., , , , , and . DSA, page 497-498. IEEE, (2019)Architecture of Cobweb-Based Redundant TSV for Clustered Faults., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (7): 1736-1739 (2020)Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 293-298. ACM, (2023)Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory., , , , , , and . VTS, page 1-6. IEEE, (2019)IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 19-24. ACM, (2024)Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique., , , , , and . ITC-Asia, page 49-54. IEEE, (2018)MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (7): 2205-2214 (July 2024)Efficient design approaches to CMOS full adder circuits., , , , , and . Microelectron. J., (2024)