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A Cross-Layer Approach for Early-Stage Power Grid Design and Optimization., , , and . JETC, 12 (3): 25:1-25:20 (2015)Early-Stage Power Grid Design: Extraction, Modeling and Optimization., , and . DAC, page 79:1-79:6. ACM, (2014)A Fast Method to Estimate Through-Bump Current for Power Delivery Verification., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (5): 1643-1647 (May 2023)On Model Order Reduction and Exponential Integrator for Transient Circuit Simulation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (1): 328-339 (January 2024)GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (10): 3492-3502 (2022)Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (5): 1450-1462 (May 2023)Worst-case Power Integrity Prediction Using Convolutional Neural Network., , , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 28 (4): 54:1-54:19 (July 2023)A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits., , , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 29 (1): 23:1-23:37 (January 2024)A Multi-Level-Optimization Framework for FPGA-Based Cellular Neural Network Implementation., , , , and . ACM J. Emerg. Technol. Comput. Syst., 14 (4): 47:1-47:17 (2018)Novel Through-Silicon-Via Inductor-Based On-Chip DC-DC Converter Designs in 3D ICs., , and . ACM J. Emerg. Technol. Comput. Syst., 11 (2): 16:1-16:14 (2014)