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Disambiguation of "Yu, Zhiyi"

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DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing.

, , , , , , , and . IEICE Electron. Express, 17 (4): 20200005 (2020)

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Zhiyi Ding

Zhiyi Lv

Yu-Ting Yu

Yu-Yu Su

Sze-Man Yu

Metal complexes with enolatoimine ligands for controlled olefin polymerizations. Uni Konstanz, (2009)
 

Other publications of authors with the same name

Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (5): 963-970 (2013)A Shared Memory Module for Asynchronous Arrays of Processors., , and . EURASIP J. Embed. Syst., (2007)A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer., , , , , and . CICC, page 1-4. IEEE, (2015)High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors., and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 66-79 (2009)Architecture and Evaluation of an Asynchronous Array of Simple Processors., , , , , , , , and . J. Signal Process. Syst., 53 (3): 243-259 (2008)Enhancing aspect-based sentiment analysis with dependency-attention GCN and mutual assistance mechanism., , and . J. Intell. Inf. Syst., 62 (1): 163-189 (February 2024)NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (9): 1966-1978 (2020)Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing., , , , and . J. Electronic Imaging, (2021)An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 311-321 (2021)A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (9): 3589-3593 (September 2023)