Author of the publication

Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance.

, , , , and . ACM Great Lakes Symposium on VLSI, page 77-83. ACM, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models., , , , and . CoRR, (2020)Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance., , , , and . ACM Great Lakes Symposium on VLSI, page 77-83. ACM, (2022)A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects., , , and . SMACD, page 89-92. IEEE, (2019)Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential., , , , and . SMACD, page 1-4. IEEE, (2023)A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees Using Matrix Exponential., , , , and . ASP-DAC, page 1-6. ACM, (2023)Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis., , , , , and . DFT, page 1-6. IEEE, (2023)EVT-based worst case delay estimation under process variation., , , and . DATE, page 1333-1338. IEEE, (2018)Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models., , , , and . ASP-DAC, page 773-778. ACM, (2021)A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees using Matrix Exponential., , , , and . CoRR, (2022)Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation., , , , and . ISQED, page 225-230. IEEE, (2020)