Author of the publication

Correlated Rare Failure Analysis via Asymptotic Probability Evaluation.

, , , , , and . DAC, page 54:1-54:6. ACM, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles., and . ISCAS (6), page 258-261. IEEE, (1999)Propagation Delay in RLC Interconnection Networks., and . ISCAS, page 2125-2128. IEEE, (1993)RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect., , , and . ISCAS, page 2710-2713. IEEE, (2007)Frequency driven repeater insertion for deep submicron., , , and . ISCAS (5), page 181-184. IEEE, (2004)Optimization of VLSI Allocation., and . ISCAS, page 1065-1068. IEEE, (1995)FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp., , , and . ASICON, page 1-4. IEEE, (2013)An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid., , , and . DATE, page 1207-1212. IEEE, (2017)Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method., , and . VLSI-SoC, page 102-105. IEEE, (2011)A DSP-based turbo codec for 3G communication systems., , , and . ICASSP, page 2685-2688. IEEE, (2002)Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design., , , , and . ICML, volume 80 of Proceedings of Machine Learning Research, page 3312-3320. PMLR, (2018)