( en | de | ru )

 

Disambiguation of "Yamasaki, Nobuyuki"

Author of the publication

copydeleteadd this publication to your clipboard
Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems.

, and . IEICE Trans. Electron., 106 (7): 365-381 (July 2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nobuyuki Kobayashi

Yuko Yamasaki

Nobuyuki Morioka

Nobuyuki Yamanaka

Takaaki Yamasaki

 

Other publications of authors with the same name

Fast Interrupt Handling Scheme by Using Interrupt Wake-Up Mechanism., and . CANDAR Workshops, page 109-114. IEEE, (2019)Global EDF-based scheduling with laxity-driven priority promotion., and . J. Syst. Archit., 57 (5): 498-517 (2011)Design and Implementation of Responsive Processor for Parallel/Distributed Control and Its Development Environments.. J. Robotics Mechatronics, 13 (2): 125-133 (2001)Space Responsive Multithreaded Processor (SRMTP) for Spacecraft Control., , , , , , and . COOL CHIPS, page 1-3. IEEE, (2020)Codeword Set Selection for the Error-Correcting 4b/10b Line Code with Maximum Clique Enumeration., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (10): 1227-1233 (2020)Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems., and . IEICE Trans. Electron., 106 (7): 365-381 (July 2023)Performance Evaluation of RUNT Algorithm., , , and . EWiLi, volume 1464 of CEUR Workshop Proceedings, CEUR-WS.org, (2015)Scheduling Imprecise Computations with Wind-up Parts., , and . CATA, page 232-235. ISCA, (2003)Design of Decoded Instruction Cache., and . CANDARW, page 159-164. IEEE, (2023)A Learning-based Fetch Thread Gating Mechanism for A Simultaneous Multithreading Processor., and . CANDAR, page 19-28. IEEE, (2020)