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DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only)., , , , , and . FPGA, page 290. ACM, (2018)Linker Code Size Optimization for Native Mobile Applications., , , , and . CoRR, (2022)The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips., , , , , , , , , and 10 other author(s). IEEE Micro, 38 (2): 30-41 (2018)Geometric Exterior Elements Calibration of Jilin-1 Linear Array Satellites Based on Star Observation., , , , and . IGARSS, page 4482-4485. IEEE, (2023)A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping., and . FPGA, page 147-156. ACM, (2017)ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests., , , , and . ICCAD, page 78-85. IEEE, (2015)CASA: correlation-aware speculative adders., , , and . ISLPED, page 189-194. ACM, (2014)FPGA HLS Today: Successes, Challenges, and Opportunities., , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 15 (4): 51:1-51:42 (2022)Rapid Generation of High-Qality RISC-V Processors from Functional Instruction Set Specifications., , and . DAC, page 122. ACM, (2019)Statistically certified approximate logic synthesis., and . ICCAD, page 344-351. IEEE, (2017)