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A clock distribution network for microprocessors., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 36 (5): 792-799 (2001)A pseudo-hierarchical methodology for high performance microprocessor design., , , , , , , , , and 8 other author(s). ISPD, page 124-129. ACM, (1997)The circuit and physical design of the POWER4 microprocessor., , , , , , , , and . IBM J. Res. Dev., 46 (1): 27-52 (2002)Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor., , , , , , , , , and 13 other author(s). ASP-DAC, page 871-878. IEEE, (2006)Low Cost Testing of High Density Logic Components., , , , , , , and . ITC, page 550-557. IEEE Computer Society, (1989)A Clock Methodology for High-Performance Microprocessors., , , , , and . VLSI Signal Processing, 16 (2-3): 217-224 (1997)Low-Cost Testing of High-Density Logic Components., , , , , , , and . IEEE Des. Test Comput., 7 (2): 15-28 (1990)