( en | de | ru )

 

Disambiguation of "Asada, Kunihiro"

Author of the publication

copydeleteadd this publication to your clipboard
Application of a continuous-time level crossing quantization method for timing noise measurements.

, , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kunihiro Jojima

 

Other publications of authors with the same name

On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems., , , , and . IEICE Trans. Electron., 96-C (4): 560-567 (2013)Noise Immunity Investigation of Low Power Design Schemes., , and . IEICE Trans. Electron., 89-C (8): 1238-1247 (2006)Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting., , , and . IEICE Trans. Electron., 101-C (4): 218-223 (2018)Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter., and . IEICE Trans. Electron., 95-C (2): 297-302 (2012)A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells., , , , and . IEICE Trans. Inf. Syst., 88-D (6): 1159-1167 (2005)A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (8): 1688-1698 (2014)A Structural Approach for Transistor Circuit Synthesis., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3529-3537 (2006)1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells., , , , and . IEICE Trans. Electron., 94-C (6): 1098-1104 (2011)Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling., , and . IEICE Trans. Electron., 95-C (4): 546-554 (2012)Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (2): 410-424 (2018)