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Disambiguation of "De, Vivek"

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A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.

, , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 42 (1): 233-242 (2007)

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Nagarajavel Vivekananthan

Vivek Venkataramani

Vivek Ramamurthy

Vivek Bose

Vivek Shetty

 

Other publications of authors with the same name

Variation-tolerant circuits: circuit solutions and techniques., , and . DAC, page 762-763. ACM, (2005)Comparative Analysis of Conventional and Statistical Design Techniques., , , , , and . DAC, page 238-243. IEEE, (2007)On-Die Supply-Resonance Suppression Using Band-Limited Active Damping., , , , , , , , , and 1 other author(s). ISSCC, page 286-603. IEEE, (2007)A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging., , , , , , and . IEEE J. Solid State Circuits, 51 (1): 117-129 (2016)A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (1): 8-19 (2018)Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits., and . IEEE J. Solid State Circuits, 48 (4): 895-896 (2013)A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 54 (12): 3316-3325 (2019)Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO., , , , , , and . IEEE J. Solid State Circuits, 55 (2): 478-493 (2020)A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS., , , , , , and . IEEE J. Solid State Circuits, 49 (4): 917-927 (2014)A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS., , , , , and . IEEE J. Solid State Circuits, 59 (1): 79-89 (January 2024)