Author of the publication

A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure.

, , , and . ISSCC, page 234-236. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique., , , and . IEEE J. Solid State Circuits, 57 (12): 3804-3815 (2022)A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 55 (2): 356-368 (2020)Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (4): 1342-1354 (2019)A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology., , , and . DAC, page 12:1-12:6. ACM, (2017)Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC., , and . ISCAS, page 1-5. IEEE, (2018)Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits., , , , and . ISPD, page 55-62. ACM, (2017)A Two-Step ADC With a Continuous-Time SAR-Based First Stage., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (12): 3375-3385 (2019)Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 784-788 (2022)A 1.11 mm2 Guidewire IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming., , , , , and . ESSCIRC, page 309-312. IEEE, (2023)Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing., , , , and . IMW, page 1-4. IEEE, (2021)