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RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design.

, , , , , , , and . SOSP, page 182-199. ACM, (2023)

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Design methodology for semi custom processor cores., , , , , and . ACM Great Lakes Symposium on VLSI, page 448-452. ACM, (2004)RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design., , , , , , , and . SOSP, page 182-199. ACM, (2023)High-Throughput, Lossless Data Compresion on FPGAs., , , and . FCCM, page 113-116. IEEE Computer Society, (2011)Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor., , , , , , , , and . MICRO, page 15-26. ACM, (2017)Reducing instruction fetch energy with backwards branch control information and buffering., , , and . ISLPED, page 322-325. ACM, (2003)Database Analytics: A Reconfigurable-Computing Approach., , , , , , and . IEEE Micro, 34 (1): 19-29 (2014)Designing a Testable System on a Chip., , , , , , , , , and 5 other author(s). VTS, page 2-7. IEEE Computer Society, (1998)Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation., , , , , , , and . FPGA, page 230. ACM, (2023)Efficient in-system RTL verification and debugging using FPGAs (abstract only)., , , , , and . FPGA, page 269. ACM, (2012)A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation., , , , , , , , , and . FPGA, page 153-162. ACM, (2012)