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Structure optimization for efficient AlN piezoelectric energy harvesters., , , , and . ICECS, page 527-530. IEEE, (2015)Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks., , , and . ISCAS, page 2752-2755. IEEE, (2014)Optimum positioning of interleaved repeaters In bidirectional buses., and . DAC, page 586-591. ACM, (2003)A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors., , , , , , , and . ICCD, page 253-257. IEEE Computer Society, (2005)Reducing the Data Switching Activity on Serial Link Buses., , , and . ISQED, page 425-432. IEEE Computer Society, (2006)Pyramidal Neuron Architectures for AcceleratingDeep Neural Networks on FPGA., , and . AHS, page 104-111. IEEE, (2018)SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (2): 384-394 (2009)Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (9): 1928-1933 (2006)Formal derivation of optimal active shielding for low-power on-chip buses., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (5): 821-836 (2006)Effect of relative delay on the dissipated energy in coupled interconnects., and . ISCAS (2), page 525-528. IEEE, (2004)