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Disambiguation of "Shirane, Atsushi"

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64QAM wireless link with 300GHz InP-CMOS hybrid transceiver.

, , , , and . IEICE Electron. Express, 18 (17): 20210314 (2021)

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Atsushi Imai

Atsushi Imai

Atsushi Yagi

Atsushi Fukui

Atsushi Kambayashi

 

Other publications of authors with the same name

A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 55 (9): 2371-2386 (2020)A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer., , , , , and . IEEE J. Solid State Circuits, 57 (4): 1211-1223 (2022)A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration., , , , , , , , , and 4 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 603-616 (2021)A Ka-Band Deployable Active Phased Array Transmitter Fabricated on 4-Layer Liquid Crystal Polymer Substrate for Small-Satellite Mount., , , , , , , , , and 4 other author(s). IEEE Access, (2023)64QAM wireless link with 300GHz InP-CMOS hybrid transceiver., , , , and . IEICE Electron. Express, 18 (17): 20210314 (2021)Wireless Devices Identification with Light-Weight Convolutional Neural Network Operating on Quadrant IQ Transition Image., , , and . NEWCAS, page 106-109. IEEE, (2020)A Compact 37-40GHz CMOS Switch-Type Phase Shifter with Fine-Tuning Stage Achieving 0.4-dB RMS Gain Error., , , , and . ICTA, page 5-6. IEEE, (2020)A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation., , , , , , , , , and 2 other author(s). ISSCC, page 90-92. IEEE, (2022)A 220-294 GHz Power Amplifier with 10-dBm Psat and 2.2% PAE in 250-nm InP DHBT., , , , , , , , , and . BCICTS, page 152-155. IEEE, (2022)22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 316-318. IEEE, (2021)