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Formal hardware/software co-verification by interval property checking with abstraction.

, , , и . DAC, стр. 510-515. ACM, (2011)

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Dominik Stoffel

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Fritz Stoffel

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Rupert Stoffel

 

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Normalization at the arithmetic bit level., , и . DAC, стр. 457-462. ACM, (2005)Arithmetic Constraints in SAT-based Property Checking., , , и . MBMV, стр. 91-100. Shaker, (2007)Equivalence checking of arithmetic circuits on the arithmetic bit level., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (5): 586-597 (2004)MetaFS: Model-driven Fault Simulation Framework., , , , , , и . DFT, стр. 1-4. IEEE, (2022)Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation., , , , , , , и . VLSI-SoC, стр. 1-6. IEEE, (2022)Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation., , , , и . MBMV, стр. 1-4. VDE/IEEE, (2022)Record & play: a structural fixed point iteration for sequential circuit verification., и . ICCAD, стр. 394-399. IEEE Computer Society / ACM, (1997)Symbolic quick error detection using symbolic initial state for pre-silicon verification., , , , , , и . DATE, стр. 55-60. IEEE, (2018)Towards the impact of state encoding on induction-based property checking., , и . MBMV, стр. 199-208. Shaker, (2003)Speculative disassembly of binary code., , и . MBMV, стр. 51-52. Shaker Verlag, (2017)