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Formal hardware/software co-verification by interval property checking with abstraction.

, , , and . DAC, page 510-515. ACM, (2011)

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An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths., , , , and . CAV, volume 5123 of Lecture Notes in Computer Science, page 473-486. Springer, (2008)Towards the impact of state encoding on induction-based property checking., , and . MBMV, page 199-208. Shaker, (2003)Proof logging for computer algebra based SMT solving., , , , and . ICCAD, page 677-684. IEEE, (2013)Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation., , and . ISVLSI, page 151-158. IEEE Computer Society, (2002)Arithmetic Reasoning in DPLL-Based SAT Solving., , and . DATE, page 30-35. IEEE Computer Society, (2004)Exploiting state encoding for invariant generation in induction-based property checking., , and . ASP-DAC, page 424-429. IEEE Computer Society, (2004)A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level., , , , , and . FDL (Selected Papers), volume 36 of Lecture Notes in Electrical Engineering, page 257-272. (2008)A computational model for SAT-based verification of hardware-dependent low-level embedded system software., , , , , and . ASP-DAC, page 711-716. IEEE, (2013)Structural FSM traversal., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (5): 598-619 (2004)Modeling of Custom-Designed Arithmetic Components for ABL Normalization., , , , , and . MBMV, page 51-60. Shaker, (2008)