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False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults.

, , и . ATS, стр. 65-68. IEEE, (2007)

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Esther Fujiwara

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Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms., , и . DISC, том 5805 из Lecture Notes in Computer Science, стр. 172-173. Springer, (2009)A Test Generation Method Based on k-Cycle Testing for Finite State Machines., , и . IOLTS, стр. 232-235. IEEE, (2019)Non-scan design for testable data paths using thru operation., , , и . ASP-DAC, стр. 313-318. IEEE, (1997)Secure scan design using shift register equivalents against differential behavior attack., , и . ASP-DAC, стр. 818-823. IEEE, (2011)Fast false path identification based on functional unsensitizability using RTL information., , , и . ASP-DAC, стр. 660-665. IEEE, (2009)Test pattern selection to optimize delay test quality with a limited size of test set., , , , и . European Test Symposium, стр. 260. IEEE Computer Society, (2010)Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System., , , и . WDAG, том 1320 из Lecture Notes in Computer Science, стр. 290-304. Springer, (1997)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , и . VLSI-SoC (Selected Papers), том 249 из IFIP, стр. 301-316. Springer, (2006)Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (5): 450-454 (2007)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , и . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)