From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

A Direct Conversion Receiver with Fast-Settling DC Offset Canceller., , , и . PIMRC, стр. 1-5. IEEE, (2007)A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS., , , , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (2): 492-499 (2015)950 MHz, -60 dB TX-Cancellation Active Directional Couplers for UHF RFID Application., , и . IEICE Transactions, 94-C (10): 1539-1547 (2011)A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique., , , , , , , , , и 17 other автор(ы). ISSCC, стр. 92-94. IEEE, (2018)A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface., , , , , , , , , и 19 other автор(ы). ESSCIRC, стр. 142-145. IEEE, (2008)20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication., , , , , , , , , и 10 other автор(ы). ISSCC, стр. 348-349. IEEE, (2014)A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR., , , , , , , , , и 8 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2020)Balanced 3-phase analog signal processing for radio communications., , , , и . ISCAS, IEEE, (2006)26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS., , , , , , и . ISSCC, стр. 436-437. IEEE, (2016)19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC., , , , , и . ISSCC, стр. 336-337. IEEE, (2016)