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True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.

J. Liberty, A. Barrera, D. Boerstler, T. Chadwick, S. Cottier, H. Hofstee, J. Rosser, and M. Tsai. IBM J. Res. Dev., (2013)

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Peter H Kunerth

Peter H Kornicker

H Peter Rodemann

Peter H Werhahn

Peter H Krämer

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ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator.J. Lee, H. Kim, S. Yoo, K. Choi, H. Hofstee, G. Nam, M. Nutter, and D. Jamsek. Proc. VLDB Endow., 10 (12): 1706-1717 (2017)PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor.M. Li, G. Chen, Q. Wang, Y. Lin, H. Hofstee, P. Stenström, and D. Zhou. IEEE Comput. Archit. Lett., 15 (1): 37-40 (2016)NASB: Neural Architecture Search for Binary Convolutional Neural Networks.B. Zhu, Z. Al-Ars, and H. Hofstee. IJCNN, page 1-8. IEEE, (2020)A hardware compilation framework for text analytics queries.R. Polig, K. Atasu, H. Giefers, C. Hagleitner, L. Chiticariu, F. Reiss, H. Zhu, and H. Hofstee. J. Parallel Distributed Comput., (2018)Feature detection for image analytics via FPGA acceleration.H. Chang, I. Jiang, H. Hofstee, D. Jamsek, and G. Nam. IBM J. Res. Dev., (2015)Introduction to the Cell multiprocessor.J. Kahle, M. Day, H. Hofstee, C. Johns, T. Maeurer, and D. Shippy. IBM J. Res. Dev., 49 (4-5): 589-604 (2005)Understanding system design for Big Data workloads.H. Hofstee, G. Chen, F. Gebara, K. Hall, J. Herring, D. Jamsek, J. Li, Y. Li, J. Shi, and P. Wong. IBM J. Res. Dev., 57 (3/4): 3 (2013)OctoRay: Framework for Scalable FPGA Cluster Acceleration of Python Big Data Applications.Z. Al-Ars, J. Petri-Koenig, J. Hoozemans, L. Dierick, and H. Hofstee. SC Workshops, page 539-546. ACM, (2023)Power Efficient Processor Architecture and The Cell Processor.H. Hofstee. HPCA, page 258-262. IEEE Computer Society, (2005)Auto-tuning Spark Big Data Workloads on POWER8: Prediction-Based Dynamic SMT Threading.Z. Jia, C. Xue, G. Chen, J. Zhan, L. Zhang, Y. Lin, and H. Hofstee. PACT, page 387-400. ACM, (2016)

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Disambiguation of "Hofstee, H. Peter"

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True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.

Please choose a person to relate this publication to

Peter H Kunerth

Peter H Kornicker

H Peter Rodemann

Peter H Werhahn

Peter H Krämer

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hofstee, H. Peter"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.

Please choose a person to relate this publication to

Peter H Kunerth

Peter H Kornicker

H Peter Rodemann

Peter H Werhahn

Peter H Krämer

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.