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Dynamic-vector execution on a general purpose EDGE chip multiprocessor.

, , , , , , , , и . ICSAMOS, стр. 18-25. IEEE, (2014)

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Billion-Transistor Architectures - Guest Editors' Introduction., и . Computer, 30 (9): 46-49 (1997)Dynamic vectorization in the E2 dynamic multicore architecture., , и . SIGARCH Comput. Archit. News, 38 (4): 27-32 (2010)Errata on "Measuring Experimental Error in Microprocessor Simulation"., , , , , , и . SIGARCH Comput. Archit. News, 30 (1): 2-4 (2002)Dark Silicon and the End of Multicore Scaling., , , , и . IEEE Micro, 32 (3): 122-134 (2012)Limited bandwidth to affect processor design., , и . IEEE Micro, 17 (6): 55-62 (1997)Memory Systems.. ACM Comput. Surv., 28 (1): 63-65 (1996)Microprocessor pipeline energy analysis., , , , и . ISLPED, стр. 282-287. ACM, (2003)Mixed-Signal Charge-Domain Acceleration of Deep Neural networks through Interleaved Bit-Partitioned Arithmetic., , , , , , , и . CoRR, (2019)Register Bank Assignment for Spatially Partitioned Processors., , , и . LCPC, том 5335 из Lecture Notes in Computer Science, стр. 64-79. Springer, (2008)Changing Interaction of Compiler and Architecture., , , , , , , , , и 1 other автор(ы). Computer, 30 (12): 51-58 (1997)