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A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies.

, , and . IEEE Des. Test Comput., 22 (4): 316-326 (2005)

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The Common Hardware and Software Object Model: CHSOM., and . PDPTA, CSREA Press, (2000)Assessing Probabilistic Timing Constraints on System Performance., , and . Des. Autom. Embed. Syst., 5 (1): 61-81 (2000)Energy-delay efficient data memory subsystems: suitable for embedded media "processing"., and . IEEE Signal Process. Mag., 22 (3): 23-37 (2005)Architecture-level performance evaluation of component-based embedded systems., and . DAC, page 396-401. ACM, (2003)Lower bound on latency for VLIW ASIP datapaths., and . ICCAD, page 261-269. IEEE Computer Society, (1999)Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling., and . DATE, page 10422-10427. IEEE Computer Society, (2003)A Tight Area Upper Bound for Slicing Floorplans., , and . VLSI Design, page 280-. IEEE Computer Society, (2000)Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance., , and . DAC, page 251-256. ACM Press, (1998)Software power estimation and optimization for high performance, 32-bit embedded processors., and . ICCD, page 328-333. IEEE Computer Society, (1998)The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs., , , and . DATE, page 676-683. IEEE Computer Society / ACM, (1999)