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Disambiguation of "Yaldiz, Soner"

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Formal verification of phase-locked loops using reachability analysis and continuization.

, , , , , and . Commun. ACM, 56 (10): 97-104 (2013)

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Soner Bulut

Soner Özgür

Maria-Draga Soneriu

Soner Özen

Soner Aksu

 

Other publications of authors with the same name

A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology., , , , , and . CICC, page 1-4. IEEE, (2015)Analog/Mixed-Signal Layout Optimization using Optimal Well Taps., , , , , , , and . ISPD, page 159-166. ACM, (2022)A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 48 (5): 1138-1150 (2013)Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (7): 1264-1277 (2008)Common-Centroid Layouts for Analog Circuits: Advantages and Limitations., , , , , , and . DATE, page 1224-1229. IEEE, (2021)Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems., , , , and . ESTIMedia, page 135-140. IEEE Computer Society, (2005)Machine Learning Techniques in Analog Layout Automation., , , , , , , , , and 3 other author(s). ISPD, page 71-72. ACM, (2021)A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS., , , , , , , , , and 5 other author(s). CICC, page 1-4. IEEE, (2012)A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (8): 2009-2017 (2013)ALIGN: A System for Automating Analog Layout., , , , , , , , , and 4 other author(s). CoRR, (2020)