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Design and evaluation of a media-oriented vector processor with a multi-banked cache memory.

, , , , and . ESTIMedia, page 78-87. IEEE, (2013)

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Enhancing Memory Bandwidth in a Single Stream Computation with Multiple FPGAs., , and . FPT, page 378-380. IEEE, (2018)Design and evaluation of a media-oriented vector processor with a multi-banked cache memory., , , , and . ESTIMedia, page 78-87. IEEE, (2013)A media-oriented vector architectural extension with a high bandwidth cache system., , , , and . COOL Chips, page 1-3. IEEE Computer Society, (2012)A cache partitioning mechanism to protect shared data for CMPs., , , , and . COOL Chips, page 1-2. IEEE Computer Society, (2016)Peachy Parallel Assignments (EduHPC 2019)., , , , , , , , , and 2 other author(s). EduHPC@SC, page 75-83. IEEE, (2019)A Directive Generation Approach Using User-Defined Rules., , , and . CANDAR, page 515-521. IEEE Computer Society, (2016)Designing an Open Database of System-Aware Code Optimizations., , and . CANDAR, page 369-374. IEEE Computer Society, (2017)3D on-chip memory for the vector architecture., , , and . 3DIC, page 1-6. IEEE, (2009)Implementation and evaluation of a distributed and cooperative load-balancing mechanism for dependable volunteer computing., , , and . DSN, page 316-325. IEEE Computer Society, (2008)CheCL: Transparent Checkpointing and Process Migration of OpenCL Applications., , , , and . IPDPS, page 864-876. IEEE, (2011)