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When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies., , , , , and . CoRR, (2019)Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections., , and . CoRR, (2023)FRCSyn Challenge at WACV 2024: Face Recognition Challenge in the Era of Synthetic Data., , , , , , , , , and 37 other author(s). CoRR, (2023)Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks., , , , , , , , and . DAC, page 1-6. IEEE, (2020)FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models., , , , , and . CoRR, (2024)Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators., , , , , , and . IEEE Trans. Computers, 70 (4): 595-605 (2021)VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks., , , , , , , , , and . IEEE Trans. Computers, 71 (11): 2717-2727 (2022)Negative Feedback Training: A Novel Concept to Improve Robustness of NVCiM DNN Accelerators., , , , and . CoRR, (2023)A Semi-Decoupled Approach to Fast and Optimal Hardware-Software Co-Design of Neural Accelerators., , , and . CoRR, (2022)On the Viability of Using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators., , , and . SOCC, page 1-6. IEEE, (2023)