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Disambiguation of "Tagliavini, Giuseppe"

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BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform With a Nine-Core Processor and BLE Connectivity.

, , , , , and . IEEE Trans. Biomed. Circuits Syst., 13 (5): 893-906 (2019)

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Giuseppe Tagliavini

Giuseppe Olivato

Giuseppe Veltri

Giuseppe Rossi

Giuseppe Amato

 

Other publications of authors with the same name

TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE., , , , , , and . DATE, page 1067-1072. IEEE, (2020)A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference., , , , , and . CoRR, (2020)A transprecision floating-point platform for ultra-low power computing., , , , and . DATE, page 1051-1056. IEEE, (2018)Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (6): 2450-2463 (2023)Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). CoRR, (2021)XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes., , , , and . CoRR, (2020)End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture., , , , , , and . CoRR, (2022)Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4516-4526 (2022)HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC., , , , , , and . DATE, page 1-6. IEEE, (2023)RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors., , , , and . SAMOS, volume 13227 of Lecture Notes in Computer Science, page 16-32. Springer, (2021)