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Disambiguation of "U., Seng-Pan"

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Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects.

, , and . IEEE Trans. Instrum. Meas., 53 (4): 1279-1288 (2004)

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Peter Seng

Stefan Seng

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Gerhard Seng

 

Other publications of authors with the same name

A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS., , , , and . A-SSCC, page 285-288. IEEE, (2017)Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems., , and . ISCAS (4), page 441-444. IEEE, (2002)A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling., , , , , and . ISCAS (1), page 1061-1064. IEEE, (2003)Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (2): 489-501 (2019)Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (6): 1819-1829 (2018)A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration., , , , and . IEEE J. Solid State Circuits, 53 (3): 850-860 (2018)60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration., , , , , , , and . IEEE J. Solid State Circuits, 52 (10): 2576-2588 (2017)A digital LDO with transient enhancement and limit cycle oscillation reduction., , , and . APCCAS, page 25-28. IEEE, (2016)20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control., , , and . ISSCC, page 342-343. IEEE, (2017)Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_cm$ -Based Switching., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 1168-1172 (2017)