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Disambiguation of "Xu, Zule"

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A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool.

, , , and . IEICE Electron. Express, 16 (19): 20190546 (2019)

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Xu Xu

Xu Xu

Martin Zuleger

Werner Zuleger

Brigitte Zuleger

 

Other publications of authors with the same name

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector., , , , and . IEICE Trans. Electron., 102-C (7): 520-529 (2019)Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (2): 476-484 (2015)An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering., , and . ESSCIRC, page 245-248. IEEE, (2022)A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise., , and . A-SSCC, page 1-4. IEEE, (2015)Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL., , and . IEICE Trans. Electron., 94-C (6): 1065-1068 (2011)An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC., , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (12): 2153-2162 (2021)23.5 A 7.6mW IR-UWB Receiver Achieving -13dBm Blocker Resilience with a Linear RF Front-End., , , , , , , , , and 1 other author(s). ISSCC, page 408-410. IEEE, (2024)A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur., , and . VLSI Circuits, page 1-2. IEEE, (2021)A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC., , , and . CICC, page 1-4. IEEE, (2013)A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS., , and . NEWCAS, page 1-4. IEEE, (2013)