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Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time.

, , , and . ICCAD, page 32-39. IEEE, (2013)

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Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time., , , and . ICCAD, page 32-39. IEEE, (2013)Performance evaluation considering mask misalignment in multiple patterning decomposition., and . ISQED, page 192-197. IEEE, (2016)A polynomial time triple patterning algorithm for cell based row-structure layout., , , , and . ICCAD, page 57-64. ACM, (2012)Triple patterning aware detailed placement with constrained pattern assignment., , , , and . ICCAD, page 116-123. IEEE, (2014)Constrained pattern assignment for standard cell based triple patterning lithography., , , , and . ICCAD, page 178-185. IEEE, (2013)Grid-to-ports clock routing for high performance microprocessor designs., , , and . ISPD, page 21-28. ACM, (2011)Layout decomposition for triple patterning lithography. University of Illinois Urbana-Champaign, USA, (2016)Crosslink insertion for variation-driven clock network construction., , and . ACM Great Lakes Symposium on VLSI, page 321-326. ACM, (2012)An efficient linear time triple patterning solver., , , and . ASP-DAC, page 208-213. IEEE, (2015)Directed Self-Assembly (DSA) Template Pattern Verification., , , , , , and . DAC, page 55:1-55:6. ACM, (2014)