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Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping.

, , , , , , , , , , and . SoCC, page 137-140. IEEE, (2006)

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An on-chip march pattern generator for testing embedded memory cores., , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (5): 730-735 (2001)SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits., , and . DAC, page 26-29. IEEE Computer Society Press, (1992)Transformation of multiple fault models to a unified model for ATPG efficiency enhancement., and . ITC, page 1-10. IEEE, (2016)An on-chip self-test architecture with test patterns recorded in scan chains., , and . ITC, page 1-10. IEEE, (2016)Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function., , and . J. Electron. Test., 38 (5): 511-525 (2022)Counter-Based Output Selection for Test Response Compaction., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (1): 152-164 (2013)Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks., , and . ITC, page 82-91. IEEE, (2022)Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis., , and . ATS, page 25-30. IEEE Computer Society, (2016)A Software-Based Test Methodology for Direct-Mapped Data Cache., , , , and . ATS, page 363-368. IEEE Computer Society, (2008)A Low-Cost Diagnosis Methodology for Pipelined A/D Converters., , and . Asian Test Symposium, page 296-301. IEEE Computer Society, (2004)