( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.

, , , и . EDCC, том 1667 из Lecture Notes in Computer Science, стр. 339-350. Springer, (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Sybille Hellebrand

Sybille Hellebrand

Sybille Hellebrand

Sybille Hellebrand

Sybille Hellebrand

 

Другие публикации лиц с тем же именем

Synthesis of Self-Testable Controllers., и . EDAC-ETC-EUROASIC, стр. 580-585. IEEE Computer Society, (1994)Fast Self-Recovering Controllers., , и . VTS, стр. 296-302. IEEE Computer Society, (1998)Analyzing and quantifying fault tolerance properties.. LATW, стр. 1. IEEE Computer Society, (2013)Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study., , , и . DFT, стр. 1-6. IEEE, (2020)Are Robust Circuits Really Robust?, и . DFT, стр. 77-77. IEEE Computer Society, (2009)The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems., и . DFT, стр. 101-108. IEEE Computer Society, (2010)Efficient Online and Offline Testing of Embedded DRAMs., , , , и . IEEE Trans. Computers, 51 (7): 801-809 (2002)Synthese vollstaendig testbarer Schaltungen. Karlsruhe University, Germany, (1991)base-search.net (ftubkarlsruhe:oai:EVASTAR-Karlsruhe.de:25491).Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair., , и . DDECS, стр. 185-190. IEEE Computer Society, (2007)Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test., и . DDECS, стр. 35-41. IEEE, (2017)