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Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering video coding applications., , , and . ICASSP (5), page 93-96. IEEE, (2005)On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform., , , , and . IEEE Trans. Circuits Syst. Video Techn., 17 (7): 814-822 (2007)Analysis and hardware architecture for global motion estimation in MPEG-4 Advanced Simple Profile., , , , and . ISCAS (2), page 720-723. IEEE, (2003)Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile., , , , and . ISCAS (2), page 301-304. IEEE, (2004)System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering., , , , and . IEEE Trans. Signal Process., 54 (10): 4004-4014 (2006)VVC In-Loop Filters., , , , , , , , , and . IEEE Trans. Circuits Syst. Video Technol., 31 (10): 3907-3925 (2021)Adaptive Loop Filtering for Video Coding., , , , , , , , , and 1 other author(s). IEEE J. Sel. Top. Signal Process., 7 (6): 934-945 (2013)One-Pass Computation-Aware Motion Estimation With Adaptive Search Strategy., , , and . IEEE Trans. Multim., 8 (4): 698-706 (2006)Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME., , , and . ICME, page 365-368. IEEE Computer Society, (2006)Video de-interlacing by adaptive 4-field global/local motion compensated approach., , , and . IEEE Trans. Circuits Syst. Video Techn., 15 (12): 1569-1582 (2005)