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Disambiguation of "Knödtel, Johannes"

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Simulating large neural networks embedding MLC RRAM as weight storage considering device variations.

, , , , , , and . LASCAS, page 1-4. IEEE, (2021)

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Johannes

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Johannes

Johannes

Johannes

 

Other publications of authors with the same name

Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools., , , and . ICECS, page 225-228. IEEE, (2019)TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs, , , , , , and . Applied Reconfigurable Computing. Architectures, Tools, and Applications, page 307--321. Cham, Springer Nature Switzerland, (2023)Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks., , , , , , , and . SAMOS, volume 13227 of Lecture Notes in Computer Science, page 401-417. Springer, (2021)Trusted Computing Architectures for IoT Devices., , , , , , , , , and 1 other author(s). ARC, volume 14553 of Lecture Notes in Computer Science, page 241-254. Springer, (2024)Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?, , and . DSD, page 247-253. IEEE, (2022)TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs., , , , , , and . ARC, volume 14251 of Lecture Notes in Computer Science, page 307-321. Springer, (2023)RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems., , , and . IEEE Access, (2021)Simulating large neural networks embedding MLC RRAM as weight storage considering device variations., , , , , , and . LASCAS, page 1-4. IEEE, (2021)A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories., , , , , and . MOCAST, page 1-6. IEEE, (2020)Datapath Optimization for Embedded Signal Processing Architectures utilizing Design Space Exploration., and . DroneSE/RAPIDO@HiPEAC, page 60-65. ACM, (2023)