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Haar Filter Hardware Architecture for the Accuracy Improvement of Stereo Vision Systems.

, , , and . ISOCC, page 401-402. IEEE, (2021)

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An accurate and cost-effective stereo matching algorithm and processor for real-time embedded multimedia systems., and . Multim. Tools Appl., 76 (17): 17907-17922 (2017)Hardware Architecture of a Haar Classifier Based Face Detection System Using a Skip Scheme., , , and . ISCAS, page 1-4. IEEE, (2021)A Fully Parallel, High-Speed BPC Hardware Architecture for the EBCOT in JPEG 2000., , , , , and . FGIT-FGCN (2), volume 120 of Communications in Computer and Information Science, page 343-346. Springer, (2010)An Efficient Interworking Architecture of a Network Processor for Layer 7 Packet Processing., , , , , and . FGIT-FGCN (1), volume 265 of Communications in Computer and Information Science, page 136-146. Springer, (2011)Haar Filter Hardware Architecture for the Accuracy Improvement of Stereo Vision Systems., , , and . ISOCC, page 401-402. IEEE, (2021)A Haar Classifier Accelerator with Reduced Multiplexer Usage., and . ISOCC, page 399-400. IEEE, (2021)A study of partitioned DIMM tree management for multimedia server systems., , and . Multim. Tools Appl., 76 (17): 17937-17954 (2017)Efficient Data Transmission Scheme among Multi-devices., , and . FGIT-FGCN, volume 56 of Communications in Computer and Information Science, page 522-527. Springer, (2009)Drivable Area Detection Method Capable of Distinguishing Vegetation Area on Country Road., and . ISOCC, page 80-81. IEEE, (2018)A census-based stereo matching algorithm with multiple sparse windows., , , and . ICUFN, page 240-245. IEEE, (2015)