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Disambiguation of "Joshi, Rajiv V."

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Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (1): 30-34 (2022)

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Rajiv Trehan

Rajiv Kumar

Paneerselvam Rajiv

Jidnyasa Joshi

Rajiv Grover

 

Other publications of authors with the same name

A scannable pulse-to-static conversion register array for self-timed circuits., , and . IEEE J. Solid State Circuits, 35 (1): 125-128 (2000)A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file., , and . IEEE J. Solid State Circuits, 34 (1): 56-67 (1999)Phase Noise Analysis of Separately Driven Ring Oscillators., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (11): 4415-4428 (2022)The resilience wall: Cross-layer solution strategies., , , , , , , , , and 3 other author(s). VLSI-DAT, page 1-11. IEEE, (2014)Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue)., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 261-264 (2016)Overview of Circuits, Systems, and Applications of Spintronics., , , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 265-278 (2016)New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology., , , , and . ISLPED, page 168-171. ACM, (2003)Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (3): 485-497 (2019)SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes., , , , , , , and . ISLPED, page 87-92. ACM, (2008)3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (11): 2094-2105 (2013)