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Scalable Synthesis and Clustering Techniques Using Decision Diagrams., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (3): 423-435 (2008)Harnessing Numerical Flexibility for Deep Learning on FPGAs., , , , , , , , , and 1 other author(s). HEART, page 1:1-1:3. ACM, (2018)An OpenCL(TM) Deep Learning Accelerator on Arria 10., , , , and . CoRR, (2017)BddCut: Towards Scalable Symbolic Cut Enumeration., , and . ASP-DAC, page 408-413. IEEE Computer Society, (2007)Harnessing the Power of FPGAs with the Intel FPGA SDK for OpenCL™., , and . IWOCL, page 19:1. ACM, (2017)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC., , , , , , , , , and 1 other author(s). FPL, page 106-110. IEEE Computer Society, (2018)DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration., , , , , , , , , and 1 other author(s). FPL, page 411-418. IEEE Computer Society, (2018)Creating High Performance Applications with Intel's FPGA OpenCL™ SDK., , , , and . IWOCL, page 11:1. ACM, (2017)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only)., , , , , , , , , and 1 other author(s). FPGA, page 287. ACM, (2018)FPGA technology mapping: a study of optimality., , and . DAC, page 427-432. ACM, (2005)