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A Dynamically Tunable Memory Hierarchy., , , and . IEEE Trans. Computers, 52 (10): 1243-1258 (2003)The Impact of Page Size and Microarchitecture on Instruction Address Translation Overhead., , , and . ACM Trans. Archit. Code Optim., 20 (3): 38:1-38:25 (September 2023)Introduction to the Special Issue on PPoPP'14., , , and . ACM Trans. Parallel Comput., 2 (4): 21:1-21:2 (2016)Software Distributed Shared Memory.. Encyclopedia of Parallel Computing, Springer, (2011)Reducing the complexity of the register file in dynamic superscalar processors., , and . MICRO, page 237-248. ACM/IEEE Computer Society, (2001)Profile-Driven Component Placement for Cluster-Based Online Services., , , , and . IEEE Distributed Syst. Online, (2004)Shielding Software From Privileged Side-Channel Attacks., , , , and . USENIX Security Symposium, page 1441-1458. USENIX Association, (2018)Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power., , , , , , , and . IEEE PACT, page 141-152. IEEE Computer Society, (2002)Towards practical page coloring-based multicore cache management., , and . EuroSys, page 89-102. ACM, (2009)TreadMarks: Distributed Shared Memory on Standard Workstations and Operating Systems., , , and . USENIX Winter, page 115-132. USENIX Association, (1994)