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11807.00962.pdf
https://arxiv.org/pdf/1807.00962.pdf
6 years ago by @loroch
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cnn
memristor
neuromorphic
cnnmemristorneuromorphic
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11806.11547.pdf
https://arxiv.org/pdf/1806.11547.pdf
6 years ago by @loroch
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FPGA
cnn
architecture
FPGAcnnarchitecture
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2Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training.
S. Kim, T. Gokmen, H. Lee, and W. Haensch. CoRR, (2017)
7 years ago by @loroch
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hardware
cnn
devices
analog
architecture
neuromorphic
hardwarecnndevicesanalogarchitectureneuromorphic
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2Fast Algorithms for Convolutional Neural Networks.
A. Lavin, and S. Gray. CVPR, page 4013-4021. IEEE Computer Society, (2016)
7 years ago by @loroch
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cnn
methods
deep_learning
decomposition
winograd
compression
cnnmethodsdeep_learningdecompositionwinogradcompression
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2Sparse Convolutional Neural Networks
B. Liu, M. Wang, H. Foroosh, M. Tappen, and M. Pensky. Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, page 806--814. (2015)
6 years ago by @loroch
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cnn
sparse
deep_learning
cnnsparsedeep_learning
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3Efficient Sparse-Winograd Convolutional Neural Networks.
X. Liu, J. Pool, S. Han, and W. Dally. CoRR, (2018)
6 years ago by @loroch
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cnn
sparse
deep_learning
winograd
cnnsparsedeep_learningwinograd
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3Device placement optimization with reinforcement learning
A. Mirhoseini, H. Pham, Q. Le, B. Steiner, R. Larsen, Y. Zhou, N. Kumar, M. Norouzi, S. Bengio, and J. Dean. arXiv preprint arXiv:1706.04972, (2017)
6 years ago by @loroch
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RNN
CNN
devices
optimization
CPU
RL
deep_learning
placement
GPU
RNNCNNdevicesoptimizationCPURLdeep_learningplacementGPU
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3SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks
P. Mousouliotis, and L. Petrou. Applied Reconfigurable Computing. Architectures, Tools, and Applications: 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings 14, page 55--66. Springer, (2018)
6 years ago by @loroch
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hardware
FPGA
cnn
architecture
quantization
compression
hardwareFPGAcnnarchitecturequantizationcompression
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2Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
M. Rhu, M. O'Connor, N. Chatterjee, J. Pool, Y. Kwon, and S. Keckler. High Performance Computer Architecture (HPCA), 2018 IEEE International Symposium on, page 78--91. IEEE, (2018)
6 years ago by @loroch
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memory
cnn
DMA
sparse
deep_learning
GPU
performance
architecture
compression
memorycnnDMAsparsedeep_learningGPUperformancearchitecturecompression
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2Escher: A cnn accelerator with flexible buffering to minimize off-chip transfer
Y. Shen, M. Ferdman, and P. Milder. Field-Programmable Custom Computing Machines (FCCM), 2017 IEEE 25th Annual International Symposium on, page 93--100. IEEE, (2017)
6 years ago by @loroch
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memory
FPGA
cnn
bandwidth
buffering
acceleration
architecture
memoryFPGAcnnbandwidthbufferingaccelerationarchitecture
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1FPGA implementation of a Convolutional Neural Network for" Wake up word" detection
O. Skafs\aa. NTNU, (2017)
6 years ago by @loroch
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FPGA
CNN
master_thesis
open_cl
deep_learning
FPGACNNmaster_thesisopen_cldeep_learning
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2Computation Error Analysis of Block Floating Point Arithmetic Oriented Convolution Neural Network Accelerator Design.
Z. Song, Z. Liu, C. Wang, and D. Wang. CoRR, (2017)
7 years ago by @loroch
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cnn
error
deep_learning
floating_point
acceleration
cnnerrordeep_learningfloating_pointacceleration
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2f-CNNx: A Toolflow for Mapping Multiple Convolutional Neural Networks on FPGAs
S. Venieris, and C. Bouganis. 2018 28th International Conference on Field Programmable Logic and Applications (FPL), page 381--3817. IEEE, (2018)
6 years ago by @loroch
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hardware
FPGA
cnn
design_automation
deep_learning
architecture
hardwareFPGAcnndesign_automationdeep_learningarchitecture
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1Accelerating Deep Convolutional Networks using low-precision and sparsity
G. Venkatesh, E. Nurvitadhi, and D. Marr. (2016)cite arxiv:1610.00324.
6 years ago by @loroch
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cnn
sparse
deep_learning
ternary
acceleration
zero_skipping
architecture
quantization
cnnsparsedeep_learningternaryaccelerationzero_skippingarchitecturequantization
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2Exploring heterogeneous algorithms for accelerating deep convolutional neural networks on FPGAs
Q. Xiao, Y. Liang, L. Lu, S. Yan, and Y. Tai. Proceedings of the 54th Annual Design Automation Conference 2017, page 62. ACM, (2017)
6 years ago by @loroch
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hardware
FPGA
CNN
winograd
architecture
hardwareFPGACNNwinogradarchitecture
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2Deep Layer Aggregation.
F. Yu, D. Wang, and T. Darrell. CoRR, (2017)
7 years ago by @loroch
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cnn
topology
aggregation
deep_learning
cnntopologyaggregationdeep_learning
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3Deconvolutional networks
M. Zeiler, D. Krishnan, G. Taylor, and R. Fergus. (2010)
6 years ago by @loroch
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cnn
deep_learning
cnndeep_learning
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11Visualizing and Understanding Convolutional Networks.
M. Zeiler, and R. Fergus. CoRR, (2013)
7 years ago by @loroch
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generalization
cnn
reliability
visualization
deep_learning
classification
generalizationcnnreliabilityvisualizationdeep_learningclassification
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2Cambricon-X: An accelerator for sparse neural networks
S. Zhang, Z. Du, L. Zhang, H. Lan, S. Liu, L. Li, Q. Guo, T. Chen, and Y. Chen. Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium on, page 1--12. IEEE, (2016)
6 years ago by @loroch
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cnn
sparse
deep_learning
performance
acceleration
architecture
cnnsparsedeep_learningperformanceaccelerationarchitecture
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1Synergy: A HW/SW Framework for High Throughput CNNs on Embedded Heterogeneous SoC
G. Zhong, A. Dubey, T. Cheng, and T. Mitra. arXiv preprint arXiv:1804.00706, (2018)
6 years ago by @loroch
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accelerator
framework
FPGA
CNN
SoC
heterogeneous
embedded
acceleratorframeworkFPGACNNSoCheterogeneousembedded
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BibSonomy

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11807.00962.pdf

11806.11547.pdf

publications (hide)38
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2Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training.

2Fast Algorithms for Convolutional Neural Networks.

2Sparse Convolutional Neural Networks

3Efficient Sparse-Winograd Convolutional Neural Networks.

3Device placement optimization with reinforcement learning

3SqueezeJet: High-level Synthesis Accelerator Design for Deep Convolutional Neural Networks

2Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks

2Escher: A cnn accelerator with flexible buffering to minimize off-chip transfer

1FPGA implementation of a Convolutional Neural Network for" Wake up word" detection

2Computation Error Analysis of Block Floating Point Arithmetic Oriented Convolution Neural Network Accelerator Design.

2f-CNNx: A Toolflow for Mapping Multiple Convolutional Neural Networks on FPGAs

1Accelerating Deep Convolutional Networks using low-precision and sparsity

2Exploring heterogeneous algorithms for accelerating deep convolutional neural networks on FPGAs

2Deep Layer Aggregation.

3Deconvolutional networks

11Visualizing and Understanding Convolutional Networks.

2Cambricon-X: An accelerator for sparse neural networks

1Synergy: A HW/SW Framework for High Throughput CNNs on Embedded Heterogeneous SoC

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