BibSonomy :: author  ::

bookmarks

publications

(16)

• Exploring power management in multi-core systems.
  Reinaldo A. Bergamaschi and Guoling Han and Alper Buyuktosunoglu and Hiren Patel and Indira Nair and Gero Dittmann and Geert Janssen and Nagu R. Dhanwada and Zhigang Hu and Pradip Bose and John A. Darringer ASP-DAC 708-713 (2008)
  to dblp by dblp on 2008-05-06 00:00:00
  | URL | BibTeX  
• Performance modeling for early analysis of multi-core systems.
  Reinaldo A. Bergamaschi and Indira Nair and Gero Dittmann and Hiren Patel and Geert Janssen and Nagu R. Dhanwada and Alper Buyuktosunoglu and Emrah Acar and Gi-Joon Nam and Dorothy Kucar and Pradip Bose and John A. Darringer and Guoling Han CODES+ISSS 209-214 (2007)
  to dblp by dblp on 2008-04-08 00:00:00
  | URL | BibTeX  
• A Power Estimation Methodology for SystemC Transaction Level Models
  N. Dhanwada and I. C. Lin and V. Narayanan CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/software Codesign and System Synthesis 142--147 (2005)
  to CODES Estimation ISSS Level Modelling Power SystemC Transaction by derkling and 1 other person on 2007-04-12 13:24:17
  | URL | BibTeX  
• A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis.
  Nagu R. Dhanwada and Adrián Núñez-Aldana and Ranga Vemuri ISCAS (6) 362-365 (1999)
  to dblp by dblp on 2007-01-02 00:00:00
  | URL | BibTeX  
• Hierarchical constraint transformation based on genetic optimization for analog system synthesis.
  Nagu R. Dhanwada and Alex Doboli and Adrián Núñez-Aldana and Ranga Vemuri Integration 39 267-290 (2006)
  to dblp by dblp on 2006-07-24 00:00:00
  | URL | BibTeX  
• Transaction Level Error Susceptibility Model for Bus Based SoC Architectures.
  I.-C. Lin and S. Srinivasan and Narayanan Vijaykrishnan and N. Dhanwada ISQED 775-780 (2006)
  to dblp by dblp on 2006-05-29 00:00:00
  | URL | BibTeX  
• Architecting voltage islands in core-based system-on-a-chip designs.
  Jingcao Hu and Youngsoo Shin and Nagu R. Dhanwada and Radu Marculescu ISLPED 180-185 (2004)
  to dblp by dblp on 2006-02-15 00:00:00
  | URL | BibTeX  
• A power estimation methodology for systemC transaction level models.
  Nagu R. Dhanwada and Ing-Chao Lin and Vijay Narayanan CODES+ISSS 142-147 (2005)
  to dblp by dblp and 1 other person on 2006-02-15 00:00:00
  | URL | BibTeX  
• SEAS: a system for early analysis of SoCs.
  Reinaldo A. Bergamaschi and Youngsoo Shin and Nagu R. Dhanwada and Subhrajit Bhattacharya and William E. Dougherty and Indira Nair and John A. Darringer and Sarala Paliwal CODES+ISSS 150-155 (2003)
  to dblp by dblp on 2006-02-15 00:00:00
  | URL | BibTeX  
• Design topology aware physical metrics for placement analysis.
  Shyam Ramji and Nagu R. Dhanwada ACM Great Lakes Symposium on VLSI 186-191 (2003)
  to dblp by dblp on 2006-02-10 00:00:00
  | URL | BibTeX