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A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, and Matteo Sonza Reorda European Test Symposium, page 153-158. IEEE Computer Society, (2011)
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On Using Machine Learning for Logic BIST.
Christophe Fagot, Patrick Girard, and Christian Landrault ITC, page 338-346. IEEE Computer Society, (1997)
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A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms.
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, and B. Rodriguez ITC, page 286-293. IEEE Computer Society, (1996)
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An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation.
D. Dumas, Patrick Girard, Christian Landrault, and Serge Pravossoudovitch ITC, page 705-713. IEEE Computer Society, (1993)
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Low power BIST design by hypergraph partitioning: methodology and architectures.
Patrick Girard, Christian Landrault, Loïs Guiller, and Serge Pravossoudovitch ITC, page 652-661. IEEE Computer Society, (2000)
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Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations.
Smriti Joshi, Anne Lombardot, Philippe Flatresse, Carmelo D'agostino, Andre Juge, Edith Beigné, and Stéphane Girard J. Low Power Electronics 8(1):113-124 (2012)
to dblp by dblp on Feb 7, 2012, 12:00 AM
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A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash.
Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, and Arnaud Virazel J. Electronic Testing 25(2-3):127-144 (2009)
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A novel scheme to reduce power supply noise for high-quality at-speed scan testing.
Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, and Laung-Terng Wang ITC, page 1-10. IEEE, (2007)
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A concurrent approach for testing address decoder faults in eFlash memories.
Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, and Jean Michel Daga ITC, page 1-10. IEEE, (2007)
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An Overview of Failure Mechanisms in Embedded Flash Memories.
Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, and Arnaud Virazel VTS, page 108-113. IEEE Computer Society, (2006)
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Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.
Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, and Arnaud Virazel VTS, page 47-52. IEEE Computer Society, (2007)
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Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.
Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, and Arnaud Virazel European Test Symposium, page 77-84. IEEE Computer Society, (2007)
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NAND flash testing: A preliminary study on actual defects.
Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, and Benoît Godard ITC, page 1. IEEE, (2009)
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A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs.
Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, and Magali Bastian ITC, page 1-10. IEEE, (2008)
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SoC Yield Improvement: Redundant Architectures to the Rescue?
Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, and Arnaud Virazel ITC, page 1. IEEE, (2008)
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A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction.
Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, and Laurent Vachez European Test Symposium, page 81-86. IEEE Computer Society, (2010)
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Parity prediction synthesis for nano-electronic gate designs.
D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, and Hans-Joachim Wunderlich ITC, page 820. IEEE, (2010)
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Is test power reduction through X-filling good enough?
F. Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, and Nisar Ahmed ITC, page 805. IEEE, (2010)
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A roaming memory test bench for detecting particle induced SEUs.
Jean Marc Gallière, Paolo Rech, Patrick Girard, and Luigi Dilillo ITC, page 810. IEEE, (2010)
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On using address scrambling to implement defect tolerance in SRAMs.
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, and Nabil Badereddine ITC, page 1-8. IEEE, (2011)
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