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dblp
No matching items.
45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications.
Subramanian S. Iyer
,
G. Freeman
,
C. Brodsky
,
A. I. Chou
,
D. Corliss
,
S. H. Jain
,
Naftali E. Lustig
,
V. McGahay
,
Shreesh Narasimha
,
James P. Norum
,
K. A. Nummy
,
Paul C. Parries
,
S. Sankaran
,
C. D. Sheraw
,
P. R. Varanasi
,
G. Wang
,
M. E. Weybright
,
X. Yu
,
E. Crabbe
, and
Paul D. Agnello
.
IBM Journal of Research and Development
55(3):5
(
2011
)
Subramanian S. Iyer
,
G. Freeman
,
C. Brodsky
,
A. I. Chou
,
D. Corliss
,
S. H. Jain
,
Naftali E. Lustig
,
V. McGahay
,
Shreesh Narasimha
,
James P. Norum
,
K. A. Nummy
,
Paul C. Parries
,
S. Sankaran
,
C. D. Sheraw
,
P. R. Varanasi
,
G. Wang
,
M. E. Weybright
,
X. Yu
,
E. Crabbe
, and
Paul D. Agnello
.
IBM Journal of Research and Development
55(3):5
(
2011
)
2 years and a month ago
by
dblp
1
dblp
dblp
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