%0 Journal Article %1 journals/jssc/HanLSJA16 %A Han, Jaeduk %A Lu, Yue %A Sutardja, Nicholas %A Jung, Kwangmo %A Alon, Elad %D 2016 %J IEEE J. Solid State Circuits %K %N 4 %P 871-880 %T Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology. %U http://dblp.uni-trier.de/db/journals/jssc/jssc51.html#HanLSJA16 %V 51

@article{journals/jssc/HanLSJA16, added-at = {2023-12-12T18:10:04.000+0100}, author = {Han, Jaeduk and Lu, Yue and Sutardja, Nicholas and Jung, Kwangmo and Alon, Elad}, biburl = {https://www.bibsonomy.org/bibtex/2a8c9f91648112b0d02706a66f1c99287/admin}, ee = {https://doi.org/10.1109/JSSC.2016.2519389}, interhash = {0e64c5b692264bb059b3ae85b2b56e51}, intrahash = {a8c9f91648112b0d02706a66f1c99287}, journal = {IEEE J. Solid State Circuits}, keywords = {}, number = 4, pages = {871-880}, timestamp = {2023-12-12T18:10:04.000+0100}, title = {Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc51.html#HanLSJA16}, volume = 51, year = 2016 }