%0 Conference Paper %1 conf/itc/MercerAR81 %A Mercer, M. Ray %A Agrawal, Vishwani D. %A Roman, Carlos M. %B ITC %D 1981 %I IEEE Computer Society %K dblp %P 561-565 %T Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. %U http://dblp.uni-trier.de/db/conf/itc/itc1981.html#MercerAR81

@inproceedings{conf/itc/MercerAR81, added-at = {2002-10-22T00:00:00.000+0200}, author = {Mercer, M. Ray and Agrawal, Vishwani D. and Roman, Carlos M.}, biburl = {https://www.bibsonomy.org/bibtex/2a7a061f746de40722de520985b51ca1a/dblp}, booktitle = {ITC}, crossref = {conf/itc/1981}, date = {2002-10-22}, description = {dblp}, interhash = {0f98fd66c532928fb020d1343d84a64b}, intrahash = {a7a061f746de40722de520985b51ca1a}, keywords = {dblp}, pages = {561-565}, publisher = {IEEE Computer Society}, timestamp = {2002-10-22T00:00:00.000+0200}, title = {Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation.}, url = {http://dblp.uni-trier.de/db/conf/itc/itc1981.html#MercerAR81}, year = 1981 }