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Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation.

, , and . ITC, page 561-565. IEEE Computer Society, (1981)

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Is there a crisis in hardware verification?. CHARME, volume 105 of IFIP Conference Proceedings, page 309-310. Chapman & Hall, (1997)Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation., , and . ITC, page 561-565. IEEE Computer Society, (1981)Model checking without hardware drivers., , and . CHARME, volume 105 of IFIP Conference Proceedings, page 127. Chapman & Hall, (1997)