Inproceedings,
13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.
I. Choi, S. Hong, K. Kim, J. Hwang, S. Woo, Y. Kim, C. Cho, E. Lee, H. Lee, M. Jung, H. Jung, J. Hwang, J. Yoon, W. Lim, H. Yoo, W. Lee, J. Oh, D. Lee, J. Lee, J. Kim, Y. Kim, S. Park, B. Ho, B. Na, H. Choi, C. Lee, S. Lee, H. Shin, Y. Lee, J. Ryu, S. Shin, S. Park, D. Lim, S. Bae, Y. Sohn, T. Oh, and S. Hwang.ISSCC, page 234-236. IEEE, (2024)
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- conf/isscc/ChoiHKHWKCLLJJHYLYLOLLKKPHNCLLSLRSPLB24
- entry type
- inproceedings
- booktitle
- ISSCC
- year
- 2024
- pages
- 234-236
- publisher
- IEEE
- crossref
- conf/isscc/2024
- ee
- https://doi.org/10.1109/ISSCC49657.2024.10454327
- isbn
- 979-8-3503-0620-0
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#ChoiHKHWKCLLJJHYLYLOLLKKPHNCLLSLRSPLB24
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%1 conf/isscc/ChoiHKHWKCLLJJHYLYLOLLKKPHNCLLSLRSPLB24
%A Choi, IkJoon
%A Hong, Seunghwan
%A Kim, Kihyun
%A Hwang, Jeongsik
%A Woo, Seunghan
%A Kim, Young-Sang
%A Cho, Cheongryong
%A Lee, Eun-Young
%A Lee, Hun-Jae
%A Jung, Min-Su
%A Jung, Hee-Yun
%A Hwang, Ju-Seong
%A Yoon, Junsub
%A Lim, Wonmook
%A Yoo, Hyeong-Jin
%A Lee, Won-Ki
%A Oh, Jung-Kyun
%A Lee, Dong-Su
%A Lee, Jong-Eun
%A Kim, Jun-Hyung
%A Kim, Young-Kwan
%A Park, Su-Jin
%A Ho, Byung-Kyu
%A Na, Byongwook
%A Choi, Hye-In
%A Lee, Chung-Ki
%A Lee, Soo-Jung
%A Shin, Hyunsung
%A Lee, Young-Kyu
%A Ryu, Jang-Woo
%A Shin, Sangwoong
%A Park, Sungchul
%A Lim, Daihyun
%A Bae, Seung-Jun
%A Sohn, Young-Soo
%A Oh, Tae-Young
%A Hwang, SangJoon
%B ISSCC
%D 2024
%I IEEE
%K dblp
%P 234-236
%T 13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#ChoiHKHWKCLLJJHYLYLOLLKKPHNCLLSLRSPLB24
%@ 979-8-3503-0620-0
@inproceedings{conf/isscc/ChoiHKHWKCLLJJHYLYLOLLKKPHNCLLSLRSPLB24,
added-at = {2024-03-19T00:00:00.000+0100},
author = {Choi, IkJoon and Hong, Seunghwan and Kim, Kihyun and Hwang, Jeongsik and Woo, Seunghan and Kim, Young-Sang and Cho, Cheongryong and Lee, Eun-Young and Lee, Hun-Jae and Jung, Min-Su and Jung, Hee-Yun and Hwang, Ju-Seong and Yoon, Junsub and Lim, Wonmook and Yoo, Hyeong-Jin and Lee, Won-Ki and Oh, Jung-Kyun and Lee, Dong-Su and Lee, Jong-Eun and Kim, Jun-Hyung and Kim, Young-Kwan and Park, Su-Jin and Ho, Byung-Kyu and Na, Byongwook and Choi, Hye-In and Lee, Chung-Ki and Lee, Soo-Jung and Shin, Hyunsung and Lee, Young-Kyu and Ryu, Jang-Woo and Shin, Sangwoong and Park, Sungchul and Lim, Daihyun and Bae, Seung-Jun and Sohn, Young-Soo and Oh, Tae-Young and Hwang, SangJoon},
biburl = {https://www.bibsonomy.org/bibtex/2608e902c42e60c0f2c9fac9b53e025da/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2024},
ee = {https://doi.org/10.1109/ISSCC49657.2024.10454327},
interhash = {05a30140e65df4dcc337858907ce6876},
intrahash = {608e902c42e60c0f2c9fac9b53e025da},
isbn = {979-8-3503-0620-0},
keywords = {dblp},
pages = {234-236},
publisher = {IEEE},
timestamp = {2024-04-09T20:43:07.000+0200},
title = {13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#ChoiHKHWKCLLJJHYLYLOLLKKPHNCLLSLRSPLB24},
year = 2024
}