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%0 Conference Paper
%1 conf/isqed/RomaDSPP05
%A Roma, Carlo
%A Daglio, Pierluigi
%A Sandre, Guido De
%A Pasotti, Marco
%A Poles, Marco
%B ISQED
%D 2005
%I IEEE Computer Society
%K dblp
%P 107-112
%T How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results.
%U http://dblp.uni-trier.de/db/conf/isqed/isqed2005.html#RomaDSPP05
%@ 0-7695-2301-3
@inproceedings{conf/isqed/RomaDSPP05,
added-at = {2023-03-23T00:00:00.000+0100},
author = {Roma, Carlo and Daglio, Pierluigi and Sandre, Guido De and Pasotti, Marco and Poles, Marco},
biburl = {https://www.bibsonomy.org/bibtex/20116b33a4f1d197fec9aefe797597111/dblp},
booktitle = {ISQED},
crossref = {conf/isqed/2005},
ee = {https://doi.ieeecomputersociety.org/10.1109/ISQED.2005.62},
interhash = {1090031f93a6569209c6a6cf23d3e26e},
intrahash = {0116b33a4f1d197fec9aefe797597111},
isbn = {0-7695-2301-3},
keywords = {dblp},
pages = {107-112},
publisher = {IEEE Computer Society},
timestamp = {2024-04-10T14:10:17.000+0200},
title = {How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results.},
url = {http://dblp.uni-trier.de/db/conf/isqed/isqed2005.html#RomaDSPP05},
year = 2005
}