%0 Journal Article %1 journals/jssc/ChoKTAKRTKD17 %A Cho, Minki %A Kim, Stephen T. %A Tokunaga, Carlos %A Augustine, Charles %A Kulkarni, Jaydeep P. %A Ravichandran, Krishnan %A Tschanz, James W. %A Khellah, Muhammad M. %A De, Vivek %D 2017 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 50-63 %T Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. %U http://dblp.uni-trier.de/db/journals/jssc/jssc52.html#ChoKTAKRTKD17 %V 52

@article{journals/jssc/ChoKTAKRTKD17, added-at = {2022-10-02T00:00:00.000+0200}, author = {Cho, Minki and Kim, Stephen T. and Tokunaga, Carlos and Augustine, Charles and Kulkarni, Jaydeep P. and Ravichandran, Krishnan and Tschanz, James W. and Khellah, Muhammad M. and De, Vivek}, biburl = {https://www.bibsonomy.org/bibtex/2543b1fd8b27fa1750f0ab1122614e84d/dblp}, ee = {https://doi.org/10.1109/JSSC.2016.2601319}, interhash = {12511416ecb6cb482bb50a84fd042577}, intrahash = {543b1fd8b27fa1750f0ab1122614e84d}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {50-63}, timestamp = {2024-04-08T10:42:20.000+0200}, title = {Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc52.html#ChoKTAKRTKD17}, volume = 52, year = 2017 }