%0 Conference Paper %1 conf/isscc/RylyakovTTPAF08 %A Rylyakov, Alexander V. %A Tierno, José A. %A Turker, Didem Zeliha %A Plouchart, Jean-Olivier %A Ainspan, Herschel A. %A Friedman, Daniel J. %B ISSCC %D 2008 %I IEEE %K dblp %P 516-517 %T A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2008.html#RylyakovTTPAF08 %@ 978-1-4244-2010-0

@inproceedings{conf/isscc/RylyakovTTPAF08, added-at = {2019-07-10T00:00:00.000+0200}, author = {Rylyakov, Alexander V. and Tierno, José A. and Turker, Didem Zeliha and Plouchart, Jean-Olivier and Ainspan, Herschel A. and Friedman, Daniel J.}, biburl = {https://www.bibsonomy.org/bibtex/2b575d8febcd6c0eee7ad7ebae9e8473c/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2008}, ee = {https://doi.org/10.1109/ISSCC.2008.4523284}, interhash = {23d0c53b83374a5b8ae58aea486be095}, intrahash = {b575d8febcd6c0eee7ad7ebae9e8473c}, isbn = {978-1-4244-2010-0}, keywords = {dblp}, pages = {516-517}, publisher = {IEEE}, timestamp = {2019-07-11T11:44:40.000+0200}, title = {A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2008.html#RylyakovTTPAF08}, year = 2008 }