%0 Journal Article %1 journals/jsa/DehyadegariMY13 %A Dehyadegari, Masoud %A Mohammadi, Siamak %A Yazdani, Nasser %D 2013 %J J. Syst. Archit. %K dblp %N 7 %P 543-550 %T Distributed fair DRAM scheduling in network-on-chips architecture. %U http://dblp.uni-trier.de/db/journals/jsa/jsa59.html#DehyadegariMY13 %V 59

@article{journals/jsa/DehyadegariMY13, added-at = {2020-02-24T00:00:00.000+0100}, author = {Dehyadegari, Masoud and Mohammadi, Siamak and Yazdani, Nasser}, biburl = {https://www.bibsonomy.org/bibtex/24454f8e661c3256c932baaf507cc04d5/dblp}, ee = {https://doi.org/10.1016/j.sysarc.2013.03.004}, interhash = {26a0513da507455f7ca877322b8fbea5}, intrahash = {4454f8e661c3256c932baaf507cc04d5}, journal = {J. Syst. Archit.}, keywords = {dblp}, number = 7, pages = {543-550}, timestamp = {2020-02-25T14:22:10.000+0100}, title = {Distributed fair DRAM scheduling in network-on-chips architecture.}, url = {http://dblp.uni-trier.de/db/journals/jsa/jsa59.html#DehyadegariMY13}, volume = 59, year = 2013 }